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VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 2 OF 16
DOCUMENT REVISION HISTORY DOCUMENT DATE DESCRIPTION REVISION FROM TO A 2005.06.24 First Release. Based on a.) Test Specification: VL-TS-PDA320240D-02 REV. A 2005.06.10 b.) VL-QUA-012B, REV. W, 2004.03.20 According to VL-QUA-012B, LCD size is middle because Unit Per Laminate=6 which is in the range of 2pcs/Laminate to 6pcs /Laminate.
CHANGED BY ZHANG YAN FANG
CHECKED BY LIU ZHI QIANG
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 3 OF 16
CONTENTS
Page No. 1. 2. 3. 3.1. 3.2. 4. 4.1. 4.2. 4.3. 4.4. 5. 6. GENERAL DESCRIPTION MECHANICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS - FOR IC ONLY ENVIRONMENTAL CONDITIONS ELECTRICAL SPECIFICATIONS INTERFACE SIGNALS TYPICAL ELECTRICAL CHARACTERISTICS TIMING SPECIFICATIONS PRECAUTION WHEN CONNECTING AND DISCONNECTING THE POWER REMARK LCD COSMETIC CONDITIONS 4 4 7 7 7 8 8 9 10 14 15 16
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 4 OF 16
VARITRONIX LIMITED
Preliminary Specification of LCD Module Type PDA320240D-02
1. General Description 320 X 240 dots. FSTN Positive Black & White Transflective LCD Graphic Module. Viewing Angle: 6 O'clock direction. Driving scheme: 1/240 Duty, 1/13 bias. `NOVATEK' NT7701 (TCP form) 160 Output LCD Segment/Common Drivers or equivalent. `NOVATEK' NT7702 (TCP form) 240 Output LCD Segment/Common Drivers or equivalent. DC/DC Converters. White LED05 backlight. FFC connection.
2.
Mechanical Specifications The mechanical detail is shown in Fig. 1(a) and summarized in Table 1 below. Table 1 Parameter Outline dimensions Viewing area Active area Display format Dot size Dot spacing Dot pitch Overall Weight Specifications 95.4(W) x 128.88(H) x 7.8 (D) (Include FFC & backlight terminals, exclude TAB) 79.78(W) x 60.58(H) 76.785(W) x 57.585(H) 320 (H) dots x 240 (V) dots 0.225(W) x 0.225(H) 0.015(W) x 0.015(H) 0.24(W) x 0.24(H) TBD Unit mm mm mm mm mm mm gram
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 5 OF 16
Figure 1(a): Module specification
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 6 OF 16
C1
COM1
LCD COMMON DRIVER EIO2 'NOVATEK' NT7702 (TCP)
. . .
COM240
240
. . . . . . . C240
PDA320240D LCD GRAPHIC DISPLAY 320 X 240 DOTS
.............................................
160 160
LP FR DISPOFF
S1
S320
SEG1
.....
SEG160
SEG161 .
....
SEG320
LCD SEGMENT DRIVER 'NOVATEK' NT7701 (TCP) DISPOFF LP 3 V0,V1,V4 DC/DC Conveters and bias voltage circuit V0,V2,V3 3 3 3
LCD SEGMENT DRIVER 'NOVATEK' NT7701 (TCP) LP XCK FR DISPOFF D0~3
VSS VDD FLM
XCK
FR
D0~3
CL1 CL2 M
D-OFF
DB0~DB3
4
A K
WHITE LED05 BACKLIGHT
Figure 1(b): Block Diagram of the module.
4
4
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 7 OF 16
3. 3.1
Absolute Maximum Ratings Electrical Maximum Ratings - for IC Only Table 2 Parameter Supply voltage range (Logic) Supply voltage (LCD) Input voltage range Symbol VDD - VSS V0 VIN Min. -0.3 -0.3 -0.3 Max. +7.0 +30.0 VDD+0.3 Unit V V V
Note: 1.) The module may be destroyed if they are used beyond the absolute maximum ratings. 2.) All voltage values are referenced to VSS= 0V.
3.2
Environmental Conditions Table 3 Operating Temperature (Topr) Min. 0C Max. +50C Storage Temperature (Tstg) (Note1) Min. Max. -20C +70C
Item
Remark
Ambient Temperature (Except Touch Panel) Humidity Vibration (IEC 68-2-6) cells must be mounted on a suitable connector Shock (IEC 68-2-27) Half-sine pulse shape
Dry
No condensation 90% max. RH for Ta 40C 3 directions Frequency: 10 55 Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. 3 directions Pulse duration: 11 ms 2 Peak acceleration: 981 m/s = 100 g Number of shocks: 3 shocks in 3 mutually perpendicular axes. Note 1: Product cannot sustain in extreme storage conditions for a long time.
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 8 OF 16
4. 4.1
Electrical Specifications Interface signals Table 4: Pin description (LCD Driver) Pin No. 1 2 Symbol FLM M Description Input/output for chip select or data of the shift register. AC signal input for LCD driving waveform -The input signal is level-shifted from logic voltage level to the LCD driver voltage level, and it controls the LCD driver circuit -Normally, inputs a frame inversion signal. The LCD driver output pin's output voltage level can be set using the shift register output signal and the FR signal. Latch pulse input/shift clock input for the shift register. Display data shift clock input for segment mode. Control input for deselect output level. Input pin for display data.
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CL1 CL2
____________
D-OFF DB0 DB1 DB2 DB3 VDD VSS VEE * VSS NC A K TP_R TP_D TP_L TP_U
Power supply for logic. Ground (0V) Positive power supply for LCD driving voltage. * Ground (0V) No connection Anode of backlight Cathode of backlight. RIGHT Input Position BOTTOM Input Position LEFT Input Position TOP Input Position
* This pin should be NC (No Connection) when Built-in DC/DC converter is used
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 9 OF 16
4.2
Typical Electrical Characteristics At Ta = 25 C, VDD = 3.0V5%, VSS = 0V. Ta=25C Table 5
Parameter Supply voltage (Logic) Supply voltage (LCD) (Build-in) Input signal voltage
Symbol VDD-VSS VLCD VIH VIL
Conditions VDD=3.0V, Ta=25C, Note 1 "High" level, Note 2 "Low" level, Note 2 Character mode, VDD = 3.0V. Ta=25C, Note (1) Checker board mode, VDD = 3.0V. Ta=25C, Note (1) Forward current =20mA Number of LED chips=1x4=4
Min. 2.85 16.3 0.8 VDD 3.0 70
Typ. 3.0 16.5 20 30 3.2 100
Max. 3.15 16.7 0.2 VDD 30 45 3.4 -
Unit V V V V mA
Supply Current (Logic & LCD)
IDD
mA V cd/m2
Supply voltage of White LED05 backlight Luminance (on the backlight surface)
VLED
Note 1: There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. Note 2: Apply to pins DB0~DB3 (or D0~D3), FLM (or EIO2), CL1 (or LP), CL2 (or XCK), DISPOFF M (or FR), and D-OFF (or DISPOFF ).
____________ _________________
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 10 OF 16
4.3
Timing Specifications Refer to Fig. 2, Segment mode characteristics (NT7701) At Ta = 0 C to +50 C, VDD = 3.0V5%, VSS = 0V. Table 6
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 11 OF 16
DB0~3
Figure 2: Timing waveform of the segment mode (NT7701)
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 12 OF 16
Refer to Fig. 3, Common mode characteristics (NT7702). At Ta = 0 C to +50 C, VDD = 3.0V5%, VSS = 0V. Table 7
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 13 OF 16
Figure 3: Timing waveform of the common mode (NT7702)
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 14 OF 16
4.4
Precaution when Connecting and Disconnecting the Power Be careful when connecting or disconnecting the power. This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur, if a voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The details are as follows: When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. We recommend that you connect a serial resistor (50-100 ) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value of the resistor in consideration of LCD display grade. In addition, when connecting the logic power supply, the logic condition of this LSI inside is insecure. Therefore connect the LCD driver power supply after resetting the logic condition of this LSI inside on /DOFF function. After that, the /DOFF cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver output pins to level VSS on the /DOFF function. After that, disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown.
Figure 4: Power sequence
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 15 OF 16
5.
Remark
VL-PS-PDA320240D-02 REV. A (PDA320240D-02) JUN/2005 PAGE 16 OF 16
6.
LCD Cosmetic Conditions a.) Reference document follow VL-QUA-012B. b.) LCD size of the product is middle.
"Varitronix Limited reserves the right to change this specification." FAX:(852) 2343-9555. URL:http://www.varitronix.com - END -

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